SCLK_AON=Val_0x0, CKEN=Val_0x0, DIV_BYPASS=Val_0x0, CLK_SEL=Val_0x0, CKDIV=Val_0x0
I2Sn Control Register
| CKDIV | I2S functional clock divisor n: Clock divided by n 0 (Val_0x0): Illegal values 1 (Val_0x1): Illegal values 2 (Val_0x2): Clock divided by 2 3 (Val_0x3): Clock divided by 3 |
| CKEN | I2S clocks enable 0 (Val_0x0): Disable clocks 1 (Val_0x1): Enable clocks |
| CLK_SEL | I2S functional clock source select 0 (Val_0x0): Select 76.8 MHz crystal-oscillator clock (76M8_CLK) 1 (Val_0x1): Select external audio clock input (AUDIO_CLK) |
| DIV_BYPASS | I2S clock divider bypass 0 (Val_0x0): Do not bypass clock divider 1 (Val_0x1): Bypass clock divider |
| SCLK_AON | I2S clock output to external device always on 0 (Val_0x0): I2S clock output (I2S_SCLK) in gated mode 1 (Val_0x1): I2S clock output (I2S_SCLK) in always on mode |